1. Field of the Invention
The present invention relates to circuits which allow computer systems to modify signal timing relationships in the hardware via programmable ports in the system, thereby allowing timing adjustments to be made without the need to modify the motherboard hardware.
2. Description of the Prior Art
On computer system like an Intel-X86 based personal computer, it is common to split up buses using bi-directional tri-state buffers, thereby reducing capacative loads on each bus. Split buses require that these buffers be enabled in the proper direction and in such a way so as to avoid violating target device timing and to avoid bus driving conflicts. Since some of the devices used in a system such as this have data hold times anywhere from 5-40 ns, and since the signals used in the data transfer protocols are mostly asynchronous, it is difficult to design a circuit which provides adequate data hold time without use of an expensive analog delay line. Connecting the write command signal directly to the enable of the tri-state buffer will cause data to violate hold time on the trailing edge. Using a string of buffers is perhaps less costly but has a wide variance of delay across operating conditions. If this delay is too short, hold time is violated; if it becomes too long, there may be bus fights resulting from overlap between transfer cycles. If the ASIC device has a clock signal, it may be used to synchronize the trailing edge of the write strobe and create a 1 clock delayed version to be used as the buffer enable. However, there may not be a clock on the ASIC due to the cost of adding such a pin and/or the clock frequency available may not be fast enough to provide resolution needed for both the minimum and maximum hold delays desired. Hence, the present invention employs a method of implementing a circuit which extends the trailing edge of the write strobe and uses this signal as the enable control on the external tri-state buffers. Furthermore, the duration of this stretching can be modified by a programmable register to provide a delay which best meets the timing requirements of all devices on the motherboard.